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rail-to-rail, very fast, 2.5 v to 5.5 v, single-supply cml comparators adcmp606/adcmp607 features fully specified rail to rail at v cc = 2.5 v to 5.5 v input common-mode voltage from ?0.2 v to v cc + 0.2 v cml-compatible output stage 1.25 ns propagation delay 50 mw @ 2.5v v cc shutdown pin single-pin control for programmable hysteresis and latch (adcmp607 only) power supply rejection > 60 db ?40c to +125c operation applications high speed instrumentation clock and data signal restoration logic level shifting or translation pulse spectroscopy high speed line receivers threshold detection peak and zero-crossing detectors high speed trigger circuitry pulse-width modulators current-/voltage-controlled oscillators automatic test equipment (ate) functional block diagram v p noninverting input v n inverting input s dn input (adcmp607 only) v cci v cco (adcmp607 only) q output q output le/hys input (adcmp607 only) adcmp606/ adcmp607 cml 05917-001 figure 1. general description the adcmp606 and adcmp607 are very fast comparators fabricated on xfcb2, an analog devices, inc. proprietary process. these comparators are exceptionally versatile and easy to use. features include an input range from v ee ? 0.5 v to v cc + 0.2 v, low noise, cml-compatible output drivers, and ttl-/cmos-compatible latch inputs with adjustable hysteresis and/or shutdown inputs. the devices offer 1.25 ns propagation delay with 2.5 ps rms random jitter (rj). overdrive and slew rate dispersion are typically less than 50 ps. a flexible power supply scheme allows the devices to operate with a single +2.5 v positive supply and a ?0.5 v to +2.7 v input signal range up to a +5.5 v positive supply with a ?0.5 v to +5.7 v input signal range. the adcmp607 features split input/output supplies with no sequencing restrictions to support a wide input signal range with independent output swing control and power savings. the cml-compatible output stage is fully back-matched for superior performance. the comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. on the adcmp607, latch and programmable hysteresis features are also provided with a unique single-pin control option. the adcmp606 is available in a 6-lead sc70 package and the adcmp607 is available in a 12-lead lfcsp package. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved.
adcmp606/adcmp607 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics............................................................. 3 timing information ......................................................................... 5 absolute maximum ratings............................................................ 6 thermal resistance ...................................................................... 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 application information................................................................ 10 power/ground layout and bypassing..................................... 10 cml-compatible output stage ............................................... 10 using/disabling the latch feature........................................... 10 optimizing performance........................................................... 10 comparator propagation delay dispersion ........................... 11 comparator hysteresis .............................................................. 11 crossover bias points................................................................. 12 minimum input slew rate requirement ................................ 12 typical application circuits ......................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 10/06revision 0: initial version
adcmp606/adcmp607 rev. 0 | page 3 of 16 specifications electrical characteristics v cci = v cco =2.5 v, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit dc input characteristics voltage range v p , v n v cc = 2.5 v to 5.5 v ?0.5 v cc + 0.2 v common-mode range v cc = 2.5 v to 5.5 v ?0.2 v cc + 0.2 v differential voltage v cc = 2.5 v to 5.5 v v cc v offset voltage v os ?5.0 +5.0 mv bias current i p , i n ?5.0 2 +5.0 a offset current ?2.0 2.0 a capacitance c p , c n 1 pf resistance, differential mode ?0.1 v to v cc 200 700 k resistance, common mode ?0.5 v to v cc + 0.5 v 100 350 k active gain a v 85 db v cci = 2.5 v, v cco = 2.5 v, v cm = ?0.2 v to +2.7 v 50 db common-mode rejection ratio cmrr v cci = 2..5 v, v cco = 5.5 v 50 db hysteresis r hys = <0.1 mv latch enable pin characteristics (adcmp606 only) v ih hysteresis is shut off 2.0 v cc v v il latch mode guaranteed ?0.2 +0.4 +0.8 v i ih v ih = v cc ?6 +6 a i ol v il = 0.4 v ?0.1 +0.1 ma hysteresis mode and timing hysteresis mode bias voltage current sink 0 a 1.145 1.25 1.35 v minimum resistor value hysteresis = 120 mv 55 75 110 k latch setup time t s v od = 50 mv ?1.5 ns latch hold time t h v od = 50 mv 2.3 ns latch-to-output delay t ploh , t plol v od = 50 mv 30 ns latch minimum pulse width t pl v od = 50 mv 25 ns shutdown pin characteristics (adcmp607 only) v ih comparator is operating 2.0 v cco v v il shutdown guaranteed ?0.2 +0.4 +0.6 v i ih v ih = v cc ?6 +6 a i ol v il = 0 v ?0.1 ma sleep time t sd 10% output swing <1 ns wake-up time t h v od = 100 mv, output valid 35 ns dc output characteristics v cco = 2.5 v to 5.5 v output voltage high level v oh ri = 50 , v cco = 2.5 v v cc ? 0.1 v cc + 0.1 v output voltage low level v ol ri = 50 , v cco = 2.5 v v cc ? 0.5 v cc ? 0.35 v minimum v cco for operation without external termination (adcmp607) t a = ?40c, v ol = v cc ? 0.7 2.7 v
adcmp606/adcmp607 rev. 0 | page 4 of 16 parameter symbol conditions min typ max unit ac performance 1 rise time /fall time t r t f 10% to 90%, v cc = 2.5 v to 5.5 v 160 ps propagation delay t pd v cc = 2.5 v to 5.5 v, v od = 50 mv, 1.2 ns v cc = 2.5 v, v od = 10 mv 2.1 ns propagation delay skewrising to falling transition t pinskew v od = 50 mv 40 ps overdrive dispersion 10 mv < v od < 125 mv 2.3 ns common-mode dispersion ?0.2 v < v cm < v cc + 0.2 v 150 ps input stage bandwidth 750 mhz rms random jitter rj v od = 200 mv, 0.5 v/ns 2 ps minimum pulse width pw min v cci = v cco = 5.5 v, pw out = 90% of pw in 1.1 ns output skew q to q t diffskew 50% 20 ps power supply input supply voltage range v cci 2.5 5.5 v output supply voltage range v cco 2.5 5.5 v positive supply differential (adcmp607) v cci ? v cco operating ?3.0 +3.0 v v cci ? v cco nonoperating ?6 +6 v positive supply current i vcc v cc = 2.5 v 11 17.5 21 ma (adcmp606) v cc = 5.5 v 16 20.5 26 ma input section supply current i vcci v cci = 2.5 v 0.5 1.1 1.5 ma (adcmp607) output section supply current i vcco v cci = 2.5 v 10 15.8 18 ma (adcmp607) i vcco v cci = 5.5 v 16 18 25 ma power dissipation p d v cc = 2.5 v 30 46 55 mw p d v cc = 5.5 v 90 110 150 mw power supply rejection ratio psrr v cci = 2.5 v to 5 v ?50 db shutdown mode i cci v cci =2.5 v to 5 v 200 240 800 a shutdown mode i cco v cci =2.5 v to 5 v ?30 30 a 1 v in = 100 mv square input at 50 mhz, v cm = 2.5 v, v cci = v cco = 2.5 v, unless otherwise noted.
adcmp606/adcmp607 rev. 0 | page 5 of 16 timing information figure 2 illustrates the adcmp606/adcmp607 latch timing relationships. table 2 provides definitions of the terms shown in figur e 2. 1.1v 50% v n v os differential input voltage latch enable q output t h t pdl t ploh t f v in v od t s t pl 50% q output t pdh t plol t r 05917-025 figure 2. system timing diagram table 2. timing descriptions smbol timing description t f output fall time amount of time required to transition from a high to a low output as measured at the 20% and 80% points. t h minimum hold time minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be ac quired and held at the outputs. t pdh input to output high delay propagation delay measured from the time th e input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. t pdl input to output low delay propagation delay measured from the time th e input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. t pl minimum latch enable pulse width minimum time that the latch enable signal must be high to acquire an input signal change. t ploh latch enable to output high delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. t plol latch enable to output low delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. t r output rise time amount of time required to transition from a low to a high output as measured at the 20% and 80% points. t s minimum setup time minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. v od voltage overdrive difference between the input voltages v a and v b .
adcmp606/adcmp607 rev. 0 | page 6 of 16 absolute maximum ratings table 3. parameter rating supply voltages input supply voltage (v cci to gnd) ?0.5 v to +6.0 v output supply voltage (v cco to gnd) ?0.5 v to +6.0 v positive supply differential (v cci ? v cco ) ?6.0 v to +6.0 v input voltages input voltage ?0.5 v to v cci + 0.5 v differential input voltage (v cci + 0.5 v) maximum input/output current 50 ma shutdown control pin applied voltage (hys to gnd) ?0.5 v to v cco + 0.5 v maximum input/output current 50 ma latch/hysteresis control pin applied voltage (hys to gnd) ?0.5 v to v cco + 0.5 v maximum input/output current 50 ma output current 50 ma temperature operating temperature, ambient ?40c to +125c operating temperature, junction 150c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja 1 unit adcmp606 sc70 6-lead 426 c/w adcmp607 lfcsp 12-lead 62 c/w 1 measurement in still air. esd caution
adcmp606/adcmp607 rev. 0 | page 7 of 16 pin configuration and fu nction descriptions q 1 v ee 2 v p 3 q 6 v cci /v cco 5 v n 4 adcmp606 top view (not to scale) 05917-002 pin 1 indicator top view (not to scale) adcmp607 v cco 1 v cci 2 v ee 3 v p 4 v ee 5 vn 6 9 v ee 8 le/hys 7 s dn 12 q 11 v ee 10 q 05917-003 figure 3. adcmp606 pin configuration figure 4. adcmp607 pin configuration table 5. adcmp606 (sc70-6) pin function descriptions pin o. mnemonic description 1 q noninverting output. q is at logic high if th e analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n . 2 v ee negative supply voltage. 3 v p noninverting analog input. 4 v n inverting analog input. 5 v cci /v cco input section supply/output se ction supply. shared pin. 6 q inverting output. q is at logic low if the analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v in . table 6. adcmp607 (lfcsp-12) pin function descriptions pin o. mnemonic description 1 v cco output section supply. 2 v cci input section supply. 3 v ee negative supply voltage. 4 v p noninverting analog input. 5 v ee negative supply voltage. 6 v n inverting analog input. 7 s dn shutdown. drive this pin low to shut down the device. 8 le/hys latch/hysteresis control. bias with resistor or current for hysteresis adjustment; drive low to latch. 9 v ee negative supply voltage. 10 q inverting output. q is at logic low if the analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , if the comparator is in compare mode. 11 v ee negative supply voltage. 12 q noninverting output. q is at logic high if th e analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , if the comparator is in compare mode. heat sink paddle v ee the metallic back surface of the package is electrically connected to v ee . it can be left floating because pin 3, pin 5, pin 9, and pin 11 provide adequate electrical connection. it can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
adcmp606/adcmp607 rev. 0 | page 8 of 16 typical performance characteristics v cci = v cco = 2.5 v, t a = 25c, unless otherwise noted. current (a) ?800 ?600 ?400 ?200 0 200 400 600 800 le/hys pin (v) ?10123456 7 05917-026 v cc = 5.5v v cc = 2.5v figure 5. le/hys pin i/v curve current (a) s dn pin (v) ?150 ?100 ?50 0 50 100 150 200 ?1 0 1 2 3 4 5 6 7 v cc = 5.5v v cc = 2.5v 05917-007 figure 6. s dn i/v curve i b (a) v cm at v cc = 2.5v ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 +125c ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 05917-006 ?40c +25c figure 7. input bias current vs. common-mode voltage 0 50 100 150 200 250 hysteresis (mv) 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?18 le/hys pin current (a) +25c +125c ?40c 05917-004 figure 8. hysteresis vs. le/hys pin current hysteresis (mv) hys resistor (k ? ) 0 50 100 150 200 250 300 350 400 50 100 150 200 250 300 350 400 450 500 550 600 650 v cc = 2.5v 05917-005 figure 9. hysteresis vs. r hys propagation delay (ns) overdrive (mv) 1.0 1.5 2.0 2.5 3.0 3.5 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 propagation delay rise propagation delay fall 05917-009 figure 10. propagation delay vs. input overdrive
adcmp606/adcmp607 rev. 0 | page 9 of 16 propagation delay (ns) v cm at v cc = 2.5v 1.1 1.2 1.3 1.4 ?0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 propagation delay fall ns propagation delay rise ns 05917-010 figure 11. propagation delay vs. input common mode 05917-011 2.050v 1.000ns/div 2.550v q q figure 12 .output waveform at v cc = 2.5 v 0 5917-012 q q 5.050v 1.000ns/div 5.550v figure 13. output waveform at v cc = 5.5 v
adcmp606/adcmp607 rev. 0 | page 10 of 16 application information power/ground layout and bypassing the adcmp606/adcmp607 comparators are very high speed devices. despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. of critical importance is the use of low impedance supply planes, particularly the output supply plane (v cco ) and the ground plane (gnd). individual supply planes are recommended as part of a multilayer board. providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. it is also important to adequately bypass the input and output supplies. multiple high quality 0.01 f bypass capacitors should be placed as close as possible to each of the v cci and v cco supply pins and should be connected to the gnd plane with redundant vias. at least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the v cc pin. high frequency bypass capacitors should be carefully selected for minimum inductance and esr. parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. cml-compatible output stage specified propagation delay dispersion performance can be achieved by using proper transmission line terminations. the outputs of the adcmp606 and adcmp607 are designed to drive 400 mv directly into a 50 cable or into transmission lines terminated using either microstrip or strip line techniques with 50 referenced to v cc . the cml output stage is shown in the simplified schematic diagram in figure 14. each output is back- terminated with 50 for best transmission line matching. q 16ma 50? q v cco gnd 05917-013 figure 14. simplified schematic diagram of cml-compatible output stage if these high speed signals must be routed more than a centimeter, then either microstrip or strip line techniques are required to ensure proper transition times and to prevent excessive output ringing and pulse width dependent propagation delay dispersion. it is also possible to operate the outputs with the internal termination only if greater output swing is desired. this can be especially useful for driving inputs on cmos devices intended for full swing ecl and pecl, or for generating pseudo pecl levels. to avoid deep saturation of the outputs and resulting pulse dispersion, v cco must be kept above the specified minimum output low level (see the electrical characteristics section). the line length driven should be kept as short as possible. using/disabling the latch feature the latch input is designed for maximum versatility. it can safely be left floating or it can be driven low by any standard ttl/cmos device as a high speed latch. in addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 v nominal and an input resistance of approximately 7000 . this allows the comparator hysteresis to be easily controlled by either a resistor or an inexpensive cmos dac. driving this pin high or floating the pin removes all hysteresis. hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected parallel to the hysteresis control resistor or current source. due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 v regardless of v cc . optimizing performance as with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. large discontinuities along input and output transmission lines can also limit the specified pulse width dispersion performance. the source impedance should be minimized as much as is practicable. high source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals; higher impedances encourage undesired coupling.
adcmp606/adcmp607 rev. 0 | page 11 of 16 comparator propagation delay dispersion the adcmp606/adcmp607 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mv to v cci ? 1 v. propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (that is, how far or how fast the input signal exceeds the switching threshold). propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instru- mentation. it is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (figure 15 and figure 16). the device dispersion is typically 2.3 ns as the overdrive varies from 10 mv to 125 mv. this specification applies to both positive and negative signals because each device has very closely matched delays for positive-going and negative-going inputs as well as very low output skews. q/q output input voltage 500mv overdrive 10mv overdrive dispersion v n v os 05917-014 figure 15. propagation delayoverdrive dispersion q/q output input voltage 10v/ns 1v/ns dispersion v n v os 05917-015 figure 16. propagation delayslew rate dispersion comparator hysteresis the addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. figure 17 shows the transfer function for a comparator with hysteresis. as the input voltage approaches the threshold (0.0 v, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +v h /2, and the new switching threshold becomes ?v h /2. the comparator remains in the high state until the new threshold, ?v h /2, is crossed from below the threshold region in a negative direction. in this manner, noise or feedback output signals centered on 0.0 v input cannot cause the comparator to switch states unless it exceeds the region bounded by v h /2. output input 0 v ol v oh +v h 2 ?v h 2 05917-016 figure 17. comparator hysteresis transfer function the customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. one limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. the external feedback network can also introduce significant parasitics that reduce high speed performance and induce oscillation in some cases. this adcmp607 comparator offers a programmable hysteresis feature that can significantly improve accuracy and stability. connecting an external pull-down resistor or a current source from the le/hys pin to gnd, varies the amount of hysteresis in a predictable, stable manner. leaving the le/hys pin disconnected or driving this pin high removes hysteresis. the maximum hysteresis that can be applied using this pin is approximately 160 mv. figure 18 illustrates typical hysteresis applied as a function of the external resistor value, and figure 7 illustrates typical hysteresis as a function of the current. hysteresis (mv) h ys resistor (k ? ) 0 50 100 150 200 250 300 350 400 50 100 150 200 250 300 350 400 450 500 550 600 650 v cc = 2.5v 05917-017 figure 18. hysteresis vs. r hys control resistor
adcmp606/adcmp607 rev. 0 | page 12 of 16 the hysteresis control pin appears as a 1.25 v bias voltage seen through a series resistance of 7 k 20% throughout the hysteresis control range. the advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. an external bypass capacitor is not recommended on the le/hys pin because it impairs the latch function and often degrades the ji tter performance of the device. as described in the using/disabling the latch feature section, hysteresis control need not compromise the latch function. crossover bias points in both op amps and comparators, rail-to-rail inputs of this type have a dual front-end design. certain devices are active near the v cc rail and others are active near the v ee rail. at some predeter- mined point in the common-mode range, a crossover occurs. at this point, normally v cc /2, the direction of the bias current reverses and the measured offset voltages and currents change. the adcmp606/adcmp607 comparators slightly elaborate on this scheme. crossover points are found at approximately 0.6 v and 1.6 v common mode. minimum input slew rate requirement with the rated load capacitance and normal good pc board design practice, as discussed in the optimizing performance section, these comparators should be stable at any input slew rate with no hysteresis. broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. with additional capacitive loading or poor bypassing, oscillation is observed. this oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics in the package and pc board. in many applications, chattering is not harmful.
adcmp606/adcmp607 rev. 0 | page 13 of 16 typical application circuits adcmp606 cml output 0.1f 2.5v to 5 v 0.1f 2k ? 2k ? input 50 ? 50 ? 05917-018 figure 19. self-biased, 50% slicer adcmp606 100 ? 50 ? 50 ? lvds cml output 3.3 v 05917-019 figure 20. lvds to cml le/hys adcmp607 5 v 82pf 10k ? 10k ? 10k ? c ontrol voltage cml output 50 ? 50 ? 05917-020 figure 21. current-controlled oscillator adcmp607 100 ? 50 ? 50 ? lvds 3.3v pecl v cco 1n4001 v cci 3.3 v 05917-021 figure 22 .fake pecl levels using a series diode input 2.5v ref input 2.5v 50m v le/hys adcmp601 150pf 10k ? 10k ? 100k ? 10k ? adcmp606 5 v cml pwm output 50 ? 50 ? 05917-022 figure 23. oscillator and pulse-width modulator 150k ? 150k ? le/hys digital input control voltage 0v to 2.5 v 74 vhc 1g07 adcmp607 50 ? 50 ? 2.5v to 5 v 05917-023 figure 24. hysteresis adjustment with latch adcmp607 50 ? 50 ? output v cco +2.5v ? 3 v v cci ?2.5v v ee 05917-024 figure 25 .ground-referenced cml with 3 v input range
adcmp606/adcmp607 rev. 0 | page 14 of 16 outline dimensions compliant to jedec standards mo-203-ab 0.22 0.08 0.30 0.15 1.00 0.90 0.70 seating plane 4 5 6 3 2 1 pin 1 0.65 bsc 1.30 bsc 0.10 max 0.10 coplanarity 0.40 0.10 1.10 0.80 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 0.46 0.36 0.26 figure 26. 6-lead thin shrink small outline transistor package (sc70) (ks-6) dimensions shown in millimeters * compliant to jedec standards mo-220-veed-1 except for exposed pad dimension. 1 0.50 bsc 0.60 max pin 1 indicator 0.75 0.55 0.35 0.25 min 0.45 top view 12 max 0.80 max 0.65 typ pin 1 indicator 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref * 1.45 1.30 sq 1.15 12 4 10 6 7 9 3 2.75 bsc sq 3.00 bsc sq 2 5 8 11 coplanarity 0.08 exposed pad (bottom view) seating plane figure 27. 12-lead lead frame chip scale package (lfcsp-vq) 3 mm 3 mm body, very thin quad (cp-12-1) dimensions shown in millimeters ordering guide model temperature range package description package option branding adcmp606bksz-r2 1 ?40c to +125c 6-lead thin shrink small outline transistor package (sc70) ks-6 g0s adcmp606bksz-rl 1 ?40c to +125c 6-lead thin shrink small outline transistor package (sc70) ks-6 g0s adcmp606bksz-reel7 1 ?40c to +125c 6-lead thin shrink small outline transistor package (sc70) ks-6 g0s adcmp607bcpz-r2 1 ?40c to +125c 12-lead lead frame chip scale package (lfcsp-vq) cp-12-1 g0h adcmp607bcpz-r7 1 ?40c to +125c 12-lead lead frame chip scale package (lfcsp-vq) cp-12-1 g0h ADCMP607BCPZ-WP 1 ?40c to +125c 12-lead lead frame chip scale package (lfcsp-vq) cp-12-1 g0h 1 z = pb-free part.
adcmp606/adcmp607 rev. 0 | page 15 of 16 notes
adcmp606/adcmp607 rev. 0 | page 16 of 16 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05917-0-10/06(0)

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